Standby biasing techniques to reduce read disturbs

ABSTRACT

Devices and techniques are disclosed herein to provide a high-voltage bias signal in a standby state of the storage system without exceeding a limited maximum standby current allowance of the storage system. The high-voltage bias signal can enable a string driver circuit in the standby state to couple a global word line to a local word line, to provide a bias to, or sink a voltage from, a pillar of a string of memory cells of the storage system in the standby state, such as to reduce read disturbances in the storage system.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.16/390,558, filed Apr. 22, 2019, which claims the benefit of priority toU.S. Application Ser. No. 62/786,930, titled “Standby Biasing Techniquesto Reduce Read Disturbs”, filed 31 Dec. 2018, all of which areincorporated herein by reference in their entirety.

BACKGROUND

Memory devices are semiconductor circuits that provide electronicstorage of data for a host system (e.g., a computer or other electronicdevice). Memory devices may be volatile or non-volatile. Volatile memoryrequires power to maintain data, and includes devices such asrandom-access memory (RAM), static random-access memory (SRAM), dynamicrandom-access memory (DRAM), or synchronous dynamic random-access memory(SDRAM), among others. Non-volatile memory can retain stored data whennot powered, and includes devices such as flash memory, read-only memory(ROM), electrically-erasable programmable ROM (EEPROM), erasableprogrammable ROM (EPROM), resistance-variable memory, such as phasechange random-access memory (PCRAM), resistive random-access memory(RRAM), or magnetoresistive random access memory (MRAM), among others.

Host systems typically include a host processor, a first amount of mainmemory (e.g., often volatile memory, such as DRAM) to support the hostprocessor, and one or more storage systems (e.g., often non-volatilememory, such as flash memory) that provide additional storage to retaindata in addition to or separate from the main memory.

A storage system, such as a solid-state drive (SSD), a Universal FlashStorage (UFS™) device, a MultiMediaCard (MMC) solid-state storagedevice, an embedded MMC device (eMMC), etc., can include a memorycontroller and one or more memory devices, including a number of dies orlogical units (LUNs). In certain examples, each die can include a numberof memory arrays and peripheral circuitry thereon, such as die logic ora die processor. The memory controller can include interface circuitryconfigured to communicate with a host (e.g., the host processor orinterface circuitry) through a communication interface (e.g., abidirectional parallel or serial communication interface). The memorycontroller can receive commands or operations from the host system inassociation with memory operations or instructions, such as read orwrite operations to transfer data (e.g., user data and associatedintegrity data, such as error data or address data, etc.) between thememory devices and the host, erase operations to erase data from thememory devices, perform drive management operations (e.g., datamigration, garbage collection, block retirement), etc.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are not necessarily drawn to scale, like numeralsmay describe similar components in different views. Like numerals havingdifferent letter suffixes may represent different instances of similarcomponents. The drawings illustrate generally, by way of example, butnot by way of limitation, various embodiments discussed in the presentdocument.

FIG. 1 illustrates an example host system including a host and a storagesystem.

FIG. 2 illustrates an example 3D NAND architecture semiconductor memoryarray.

FIG. 3 illustrates generally a portion of a storage system including astandby bias circuit, a standby voltage generator circuit, a selectcircuit, and a string driver circuit.

FIG. 4 illustrates example waveforms of the portion of the storagesystem illustrated in FIG. 3.

FIG. 5 illustrates an example method of operating portions of a storagesystem including a voltage generator circuit.

FIG. 6 illustrates an example schematic diagram of a 3D NANDarchitecture semiconductor memory array.

FIG. 7 illustrates an example block diagram of a memory module.

FIG. 8 illustrates a block diagram of an example machine upon which anyone or more of the techniques discussed herein may perform.

DETAILED DESCRIPTION

Software (e.g., programs), instructions, operating systems (OS), andother data are typically stored on storage systems and accessed by mainmemory for use by a host processor. Main memory (e.g., RAM) is typicallyfaster, more expensive, and a different type of memory device (e.g.,volatile) than a majority of the memory of the storage systems (e.g.,non-volatile, such as an SSD, a UFS, an eMMC, etc.). In addition to themain memory, host systems can include different levels of volatilememory, such as a group of static memory (e.g., a cache, often SRAM),often faster than the main memory, in certain examples configured tooperate at speeds close to or exceeding the speed of the host processor,but with lower density and higher cost than the main memory. In otherexamples, more or less levels or quantities of main memory or staticmemory can be used, depending on desired host system performance, size,complexity, or cost.

Data is stored in a memory cell of a flash memory device as a particularvoltage with respect to one or more voltage thresholds. However, forvarious reasons, the particular voltage of the memory cell can shiftover time with respect to the one or more voltage thresholds, such thatthe data stored in the cell changes. Changes in data associated withread operations are referred to as read disturbance (disturb) errors.Common causes of read disturb errors include voltage shifts of memorycells associated with read or program operations (e.g., unselected cellscoupled to a selected word line or bit line due to cross-coupling,etc.), temperature-related changes or shifts to memory cells properties(e.g., current versus voltage curves, etc.), etc.

To reduce the risk of read disturb errors, error detection andcorrection can be implemented, such as by a memory controller. When anoperational threshold associated with a read error is exceeded (e.g., anumber of read errors detected in a specific portion of the memory, in atime period, etc.), associated data can be corrected and re-written toanother portion of the memory device. However, error correction is aresource intensive operation that otherwise reduces the performance ofthe memory device.

To preempt the need for error correction, wear leveling can be performedon the memory device, where, after a number of read commands have beenperformed on a portion (e.g., a block, etc.) of the memory device, thedata stored on that portion can be rewritten to another portion of thememory device to prevent subsequent data corruption or errors. Thepresent inventors have recognized, among other things, standby biasingtechniques to further reduce read disturbances (disturbs) innon-volatile memory.

Solid-state non-volatile memories (e.g., 3D NAND, Cross Point, etc.)used in solid-state drives (SSDs), pen drives (flash drives), or one ormore other storage systems using Universal Serial Bus (USB), serial ATA™(Serial AT (Advanced Technology) Attachment, or SATA), Non-VolatileMemory Express (NVMe), etc., commonly alternate in operation between anactive state (where the storage system is used for read/write/eraseoperations) and a standby state (where the storage system is in astandby low-power state). The total current allowed in the standby state(the maximum standby current) is often limited, such as by productdatasheet specs or other requirements, further limiting the availableinternal voltage of the storage system in the standby state. In anexample, the maximum standby current can be 20 uA (e.g., averaged over atime period).

In the active state, storage systems rely on voltage generators (e.g.,charge pumps) to generate high voltages required to turn on certaincomponents required to access particular memory cells of a memory device(and prevent access to other memory cells). Voltage generators canconsume large amounts of current to generate these high voltages, andthus, the voltage generators used in the active state are often disabledin the standby state to meet or stay below the limited maximum standbycurrent allowance. Accordingly, the maximum available voltage of thestorage system in the standby state can be limited to a low-voltage,internal VCC (e.g., between 2V and 3.6V, but commonly around 2V).

Memory cells in a memory device are selected using, among other things,access lines (e.g., word lines) and data lines (e.g., bit lines). Accesslines and data lines can include global lines and local lines acrossstorage systems or memory devices. In certain examples, when word linesare grounded after a read operation (and recovery phase), a channel,such as a channel of a string of memory cells associated with thegrounded word lines, may couple negative, stressing upper leveldistributions of a memory cell (e.g., level 15 (L15) in a QLC memorycell, etc.) in the standby state. In contrast, word lines not groundedafter a read operation (and recover phase) may be left floating at areset level (e.g., ^(˜)4V), stressing lower level distributions of amemory cell (e.g., level 0 (L0), etc.) in the standby state. Such upperand lower level stresses may cause voltage threshold shifts similar to aprogramming operation. To reduce such concerns, a bias voltage can beapplied to the word line in the standby state, in certain examples, highenough to not allow the channel to couple negative, and low enough tosink any floating voltage while not requiring significant current draw.

In an example, a first voltage generator with sinking and sourcingcapabilities can generate and provide a bias voltage (e.g., greater than0V and less than the reset level, such as 2V, etc.) to a global wordline (GWL) in the standby state. The GWL can be selectively connected toone or more local word lines (LWL) during the standby state using astring driver circuit, such as to mitigate first page read errors (wherea first page or a portion of memory is read repeatedly) or latent readdisturb errors (e.g., extended retention, etc.) associated with certainmemory array architectures (e.g., floating gate (FG) architecture,charge trap (e.g., replacement gate (RG)) architecture, etc.) in memorycells coupled to the LWL.

However, string driver circuits are often high-voltage (HV) devices thatrequire a voltage above an internal VCC (e.g., 5V or greater, between 4Vand 8V, etc.) to enable (e.g., transition from a high-impedance “off”state to a low-impedance “on” state). Internal VCC (e.g., in a standbystate) often ranges between 2.6V and 3.6V. High voltage, as used herein,can refer to any voltage magnitude greater than internal VCC of thememory circuit or the voltage available to the memory device during thestandby state. Low voltage, in contrast, can refer to any voltagemagnitude less than or equal to internal VCC.

The present inventors have recognized, among other things, systems,apparatus, and methods to provide a high-voltage output configured toenable a string driver circuit in a standby state of a storage system ora memory device without exceeding the limited maximum standby currentallowed by the storage system or the memory device in the standby state.

FIG. 1 illustrates an example system (e.g., a host system) 100 includinga host 105 and a storage system 110 configured to communicate over acommunication interface (I/F) 115 (e.g., a bidirectional parallel orserial communication interface). The host 105 can include a hostprocessor 106 (e.g., a host central processing unit (CPU) or otherprocessor or processing device) or other host circuitry (e.g., a memorymanagement unit (MMU), interface circuitry, etc.). In certain examples,the host 105 can include a main memory 108 (e.g., DRAM, etc.) andoptionally, a static memory 109, to support operation of the hostprocessor 106.

The storage system 110 can include a solid-state drive (SSD), auniversal flash storage (UFS) device, an embedded MMC (eMMC) device, orone or more other memory devices. For example, if the storage system 110includes a UFS device, the communication interface 115 can include aserial bidirectional interface, such as defined in one or more JointElectron Device Engineering Council (JEDEC) standards (e.g., JEDECstandard D223D (JESD223D), commonly referred to as JEDEC UFS HostController Interface (UFSHCI) 3.0, etc.). In another example, if thestorage system 110 includes an eMMC device, the communication interface115 can include a number of parallel bidirectional data lines (e.g.,DAT[7:0]) and one or more command lines, such as defined in one or moreJEDEC standards (e.g., JEDEC standard D84-B51 (JESD84-A51), commonlyreferred to as JEDEC eMMC standard 5.1, etc.). In other examples, thestorage system 110 can include one or more other memory devices, or thecommunication interface 115 can include one or more other interfaces,depending on the host 105 and the storage system 110.

The storage system 110 can include a memory controller 111 and anon-volatile memory 112. In an example, the non-volatile memory 112 caninclude a number of memory devices (e.g., dies or LUNs), such as one ormore flash memory devices, etc., each including periphery circuitrythereon, and controlled by the memory controller 111. Flash memorydevices typically include one or more groups of one-transistor memorycells. Two common types of flash memory array architectures include NANDand NOR architectures. Memory cells in the memory array are typicallyarranged in a matrix. The gates of each memory cell in a row of thearray are coupled to an access line (e.g., a word line). In NORarchitecture, the drains of each memory cell in a column of the arrayare coupled to a data line (e.g., a bit line). In NAND architecture, thedrains of each memory cell in a column of the array are coupled togetherin series, source to drain, between a source line and a bit line.

In three-dimensional (3D) architecture semiconductor memory devicetechnology, vertical floating gate (FG) or charge trap (e.g.,replacement gate (RG)) storage structures can be stacked, increasing thenumber of tiers, physical pages, and accordingly, the density of memorycells in a memory device. Each memory cell in a NOR, NAND, 3D CrossPoint, HRAM, MRAM, or one or more other architecture semiconductormemory array can be programmed individually or collectively to one or anumber of programmed states. A single-level cell (SLC) can represent onebit of data per cell in one of two programmed states (e.g., 1 or 0). Amulti-level cell (MLC) can represent two or more bits of data per cellin a number of programmed states (e.g., 2^(n), where n is the number ofbits of data). In certain examples, MLC can refer to a memory cell thatcan store two bits of data in one of 4 programmed states. A triple-levelcell (TLC) can represent three bits of data per cell in one of 8programmed states. A quad-level cell (QLC) can represent four bits ofdata per cell in one of 16 programmed states. In other examples, MLC canrefer to any memory cell that can store more than one bit of data percell, including TLC and QLC, etc.

The non-volatile memory 112 (e.g., a 3D NAND architecture semiconductormemory array) can include a number of memory cells arranged in, forexample, a number of devices, planes, blocks, or physical pages. As oneexample, a TLC memory device can include 18,592 bytes (B) of data perpage, 1536 pages per block, 548 blocks per plane, and 4 planes perdevice. As another example, an MLC memory device can include 18,592bytes (B) of data per page, 1424 pages per block, 548 blocks per plane,and 4 planes per device, but with half the required write time and twicethe program/erase (P/E) cycles as a corresponding TLC memory device.Other examples can include other numbers or arrangements.

The memory controller 111 can receive instructions from the host 105,and can communicate with the non-volatile memory 112, such as totransfer data to (e.g., write or erase) or from (e.g., read) one or moreof the memory cells of the non-volatile memory 112. The memorycontroller 111 can include, among other things, an application specificintegrated circuit (ASIC), a field programmable gate array (FPGA), orone or more other processing circuits or firmware, such as a number ofcomponents or integrated circuits. For example, the memory controller111 can include one or more memory control units, circuits, orcomponents configured to control access across the memory array and toprovide a translation layer between the host 105 and the storage system110.

The storage system 110 further includes a voltage generator circuit 102,such as a standby voltage generator circuit configured to receive alow-voltage internal VCC (e.g., a voltage available in the storagesystem 110 in a standby state), and to provide a high-voltage (HV)output configured to turn on a string driver circuit of the storagesystem 110 in the standby state, such as to bias a positive voltage to,or sink floating voltage from, one or more word lines of thenon-volatile memory 112, without exceeding a maximum standby currentallowance of the storage system 110.

In operation, in the example of NAND-based storage, data is typicallywritten to or read from the storage system 110 in “pages” and erased in“blocks.” However, one or more memory operations (e.g., read, write,erase, etc.) can be performed on larger or smaller groups of memorycells, as desired. For example, a partial update of tagged data from anoffload unit can be collected during data migration or garbagecollection to ensure it was re-written efficiently. The data transfersize of the NAND memory device is typically referred to as a page,whereas the data transfer size of a host is typically referred to as asector. Although a page of data can include a number of bytes of userdata (e.g., a data payload including a number of sectors of data) andits corresponding metadata, the size of the page often refers only tothe number of bytes used to store the user data. As an example, a pageof data having a page size of 4 KB may include 4 KB of user data (e.g.,8 sectors assuming a sector size of 512B) as well as a number of bytes(e.g., 32B, 54B, 224B, etc.) of metadata corresponding to the user data,such as integrity data (e.g., error detecting or correcting code data),address data (e.g., logical address data, etc.), or other metadataassociated with the user data.

Different types of memory cells or memory arrays can provide differentsize units in which data may be read, written, and erased, and incertain examples may require different amounts of metadata associatedtherewith. For example, different memory device types may have differentbit error rates, which can lead to different amounts of metadatanecessary to ensure integrity of the page of data (e.g., a memory devicewith a higher bit error rate may require more bytes of error correctioncode data than a memory device with a lower bit error rate). As anexample, an MLC NAND flash device may have a higher bit error rate thana corresponding SLC NAND flash device, and as such, may require morebytes for error data than the corresponding SLC device.

FIG. 2 illustrates an example 3D NAND architecture semiconductor memoryarray 200 including N word lines 201 and first and second select gates202, 203, stacked between a source line 204 and M bit lines 205.Multiple pillars extend through the word lines 201 to create memorycells. Due to process (e.g., side and etching effects), the pillardiameter may be irregular (e.g., irregular between the multiple pillars,irregular as each pillar extends through the stacked word lines 201,etc.). Moreover, each word line can vary (e.g., in size, in surfacevariations, etc.). Accordingly, electrical parameters (e.g., resistance,capacitance, etc.) of each word line can vary with respect to the stack,affecting performance of the memory cells. Although illustrated hereinas 5 word lines and 7 bit lines, memory arrays frequently have largenumbers of each (e.g., 64, 92, 128, etc.). Electrical parameters of bitlines can also vary; however, such variance is often less than thatfound in word lines.

FIG. 3 illustrates generally a portion of a storage system 300 includinga standby bias circuit 301, a standby voltage generator circuit 302, aselect circuit 306, and a string driver circuit 307. The standby biascircuit 301 can be configured to provide a standby bias voltage (e.g., alow-voltage output) to a global word line (GWL) 308 in a standby stateof the storage system 300. In certain examples, the standby bias circuit301 can have sinking and sourcing capabilities, such as to provide apositive (non-negative) bias, while also removing any stored voltage(e.g., floating voltage, etc.), such as from a coupled word line, etc.,while not using excess power. In an example, the standby bias circuit301 can provide an internal, low-voltage source (internal VCC) (e.g., 2V), such that the standby bias voltage is a low-voltage output. In otherexamples, the internal VCC can range between 2V and 3.6V, and thestandby bias circuit 301 can be configured to provide a standby biasvoltage lower than internal VCC (e.g., ^(˜)2V or lower, 3V or lower,etc.).

The standby voltage generator circuit 302 can include a voltagegenerator (VOLT GEN) 303, such as a charge pump circuit or one or moreother voltage generator circuits, configured to receive an input voltage(IN), such as from an internal, low-voltage source (internal VCC), andprovide an output voltage (OUT) higher than the input voltage, such as ahigh-voltage output greater than internal VCC. In an example, the outputvoltage can be greater than any voltage source provided by the storagesystem in the standby state. In an example, the input voltage can bebetween 2V and 3.6V, and the output voltage can be greater than 4V(e.g., between 4V and 8V, etc.). The voltage generator 303 can becontrolled by a voltage generator control circuit (VG CTRL) 304, whichcan receive one or more clock signals from an oscillator circuit 305.

In an example, the voltage generator control circuit 304 can beconfigured to receive information from, or provide information to, thememory controller, the host processor, or one or more components of thestorage system or host device, such as to control one or more functionsor components of the standby voltage generator circuit 302. In otherexamples, one or more functions of the voltage generator control circuit304 or the oscillator can be implemented using the memory controller orother component of the storage system. The voltage generator controlcircuit 304 can include a counter, counter logic, one or more statemachines, or a controller configured to count clock signals, compare thecount to certain thresholds, and to transition to other states withother logic, functions, or counters. In an example, the standby voltagegenerator circuit 302 can control the standby bias circuit 301, such asto selectively provide the bias with sinking and sourcing capabilitieswhen the voltage generator 302 provides the output voltage. In otherexamples, the standby bias circuit 301 can be configured to power thestandby voltage generator circuit 302.

The select circuit 306 can include one or more block selector or decodercircuit (e.g., a row decoder, etc.) configured to provide selectableaccess to a string driver circuit 307 (or a number of selectable stringdriver circuits). The string driver circuit 307 can be configured tocouple the GWL 308 to a local word line (LWL) 309 (or a selectablenumber of LWLs) in a first, low-impedance, conductive state (e.g., an“on” state), or electrically isolate the GWL 308 from the LWL 309 in asecond, high-impedance, non-conductive state (e.g., an “off” state). Inan example, the string driver circuit 307 can be a high-voltage (HV)device that requires a voltage above an internal VCC to be enabled.

In certain examples, such as in an active state of the storage system300, high voltages can be applied to the GWL 308 or the LWL 309 (e.g.,15V or higher for certain memory operations). Accordingly, in certainexamples, the select circuit 306 can include HV level-shift components,including HV PMOS or depletion-mode transistors (HVP, HVD) or other HVcomponents. Further, in certain examples, certain electrical propertiesof such HV components (e.g., threshold voltages, etc.) can shift, suchas due to degradation of one or more components of the select circuit306 (e.g., voltage threshold shifts of an HVP device can be ^(˜)3V afterextended periods, such as 10 years, etc.). Accordingly, a high-voltagesignal can be required to turn on the select circuit 306 and thereforethe string driver circuit 307, however, without exceeding the limitedmaximum standby current allowed in the standby state, which, in certainexamples, can be 20 uA or lower.

In certain examples, voltage generators can provide an HV output signal(e.g., ^(˜)5V, between 4V and 8V, etc.) using less than 20 uA, and incertain examples, as low as 5 uA. However, in application, voltagegenerator (e.g., charge pump) inefficiency can approach 10× or more incertain conditions, risking a consumption from VCC supply of 50 uA ormore with a 5 uA internal current capability. To further reduce thestandby current, the present inventors have recognized that the standbystate can be further divided into an active period and a refresh period.

Further, in certain examples, the oscillator circuit 305 can include oneor more oscillators configured to provide different clock signals to thevoltage generator control circuit 304, and accordingly, to the voltagegenerator 303, in the different portions of the standby state, includinga low-power clock signal (e.g., a sample and hold clock signal) in therefresh period of the standby state and a second, higher-power clocksignal (e.g., with a higher frequency than the low-power clock signal, afaster start-up time, etc.) in the active period of the standby state.

During the refresh period, the standby bias circuit 301 can provide alow-voltage output (e.g., 2V) and the voltage generator 303 can receivethe input signal and build an HV output, to be provided at the activeperiod of the standby state. In an example, the active period of thestandby state can be as little as several microseconds (e.g., 15 us,etc.). The refresh period can be longer than the active period, incertain examples, by a substantial margin, such as hundreds ofmicroseconds, milliseconds, or tens or hundreds of milliseconds. Ingeneral, to reduce the average current consumption of the voltagegenerator circuit 302, it is beneficial to reduce the active period incontrast to the refresh period, while still providing a bias to, orsinking voltage from, one or more selected word lines. Further, incertain examples, the voltage generator 303 can build and provide the HVoutput entirely during the active period, or the voltage generator 303can build the HV output during the refresh period, or a combination ofthe refresh period and the active period, while providing the HV outputduring at least a portion of the active period.

FIG. 4 illustrates example waveforms 400 of the portion of the storagesystem illustrated in FIG. 3. In an example, at a first time (T1), alow-voltage (LV) internal VCC (e.g., 2V) 401 can be enabled andprovided, such as in preparation for or upon entry into a standby stateof a storage system. At a second time (T2), a refresh time of a voltagegenerator circuit can be enabled having a refresh period 402. Thevoltage generator can build a high-voltage (HV) output signal (e.g., atleast 4V, between 4V and 8V (or higher)) 403. At a third time (T3), theHV output signal is provided for an active period 404, high enough toenable a string driver circuit to couple a global word line to a localword line. In an example, the LV internal VCC can be provided to theglobal word line that, when coupled to the local word line, activelybiases the local word line, or sinks a voltage (e.g., a floatingvoltage) from the word line. Refresh and active periods can repeat atfixed or varying intervals (e.g., a second refresh period 402 begins ata fourth time (T4), and a second active period 404 begins at a fifthtime (T5), both ending at a sixth time (T6), etc.) until the standbystate of the storage system is disabled at a seventh time (T7).

The refresh period 402 can be longer than the active period 404, incertain examples, by a substantial margin (e.g., 8X, 16X, 64X, 512X,4096X, etc.), depending on the word line source/sink or standby currentrequirements. In general, a wider active period 404 requires a smallermargin in contrast to the refresh period 402. Further, the clock periodof the oscillator, a threshold of a counter used to determine the activeand refresh periods, etc., can be adjusted using one or more selectabletrim values to provide different refresh periods and standby currentdraw. In certain examples, the standby current impact (e.g., averagecurrent draw over time, maximum current draw, etc.) can be in tens of nA(e.g., 8-10 nA), or if a smaller refresh period is desired, −1-10 uA.However, at a certain point, voltage generator inefficiency variance maybecome an issue. Accordingly, it can be beneficial to stay below themaximum standby current allowance (e.g., 20 uA) by a factor of 10×(e.g., <2 uA). In certain examples, the maximum standby currentallowance can be an average current allowance, or in other examples, anallowed current magnitude.

Although illustrated in FIG. 4 as a square wave, in practice, thevoltage generated by the voltage generator circuit will peaksubstantially above HV, settling to HV at the end of the active period404, depending on, for example, diffusion leakage, selected capacitors,etc., of one or more of the voltage generator or the string drivercircuit. For example, the voltage of the active period 404 can rise to8V or higher, settling to 4.5V. In other examples, other voltages can bereached, depending on circuit design and current requirements.

FIG. 5 illustrates an example method 500 of operating portions of astorage system including a voltage generator circuit, such as thatillustrated the example of FIG. 3. At 501, the method 500 waits for anenable signal. In an example, the method can be enabled upon the storagesystem receiving an instruction to enter or otherwise entering a standbystate. At 502, a decision to boost an internal, low-voltage VCCproviding in the standby state to an HV output can be received.

At 503, a first count can be incremented, such as using a clock signaland logic of a voltage generator control circuit. At 504, the firstcount can be compared to a first target. During the first count,capacitors or capacitive elements of a voltage generator (e.g., a chargepump) can be charged. When the first target is reached, the voltagegenerator can be enabled at 505, providing an HV output at an output ofthe voltage generator.

At 506, a second count can be incremented, such as using a clock signal(e.g., the same as or different than the clock signal used for the firstcount). In an example, the voltage generator can include a standardclock/oscillator (e.g., selectable) once enabled, however, a separatelow-power oscillator can be used for the first count, which is amajority of the time of the method 500. At 507, the second count can becompared to a second target. When the second target is reached, thevoltage generator can be disabled at 508, and process can return to theenable decision at 501.

FIG. 6 illustrates an example schematic diagram of a 3D NANDarchitecture semiconductor memory array 600 including a number ofstrings of memory cells (e.g., first-third A₀ memory strings605A₀-607A₀, first-third A_(n) memory strings 605A_(n)-607A_(n),first-third B₀ memory strings 605B₀-607B₀, first-third B_(n) memorystrings 605B_(n)-607B_(n), etc.), organized in blocks (e.g., block A601A, block B 601B, etc.) and sub-blocks (e.g., sub-block A₀ 601A₀,sub-block A_(n) 601A_(n), sub-block B₀ 601B₀, sub-block B_(n) 601B_(n),etc.). The memory array 600 represents a portion of a greater number ofsimilar structures that would typically be found in a block, device, orother unit of a memory device.

Each string of memory cells includes a number of tiers of charge storagetransistors (e.g., floating gate transistors, charge-trappingstructures, etc.) stacked in the Z direction, source to drain, between asource line (SRC) 635 or a source-side select gate (SGS) (e.g.,first-third A₀ SGS 631A₀-633A₀, first-third A_(n) SGS 631A_(n)-633A_(n),first-third B₀ SGS 631B₀-633B₀, first-third B_(n) SGS 631B_(n)-633B_(n),etc.) and a drain-side select gate (SGD) (e.g., first-third A₀ SGD626A₀-628A₀, first-third A_(n) SGD 626A_(n)-628A_(n), first-third B₀ SGD626B₀-628B₀, first-third B_(n) SGD 626B_(n)-628B_(n), etc.). Each stringof memory cells in the 3D memory array can be arranged along the Xdirection as data lines (e.g., bit lines (BL) BL0-BL6 620-622), andalong the Y direction as physical pages.

Within a physical page, each tier represents a row of memory cells, andeach string of memory cells represents a column. A sub-block can includeone or more physical pages. A block can include a number of sub-blocks(or physical pages) (e.g., 128, 256, 384, etc.). Although illustratedherein as having two blocks, each block having two sub-blocks, eachsub-block having a single physical page, each physical page having threestrings of memory cells, and each string having 8 tiers of memory cells,in other examples, the memory array 600 can include more or fewerblocks, sub-blocks, physical pages, strings of memory cells, memorycells, or tiers. For example, each string of memory cells can includemore or fewer tiers (e.g., 16, 32, 64, 128, etc.), as well as one ormore additional tiers of semiconductor material above or below thecharge storage transistors (e.g., select gates, data lines, etc.), asdesired. As an example, a 48 GB TLC NAND memory device can include18,592 bytes (B) of data per page (16,384+2208 bytes), 1536 pages perblock, 548 blocks per plane, and 4 or more planes per device.

Each memory cell in the memory array 600 includes a control gate (CG)coupled to (e.g., electrically or otherwise operatively connected to) anaccess line (e.g., word lines (WL) WL0 ₀-WL7 ₀ 610A-617A, WL0 ₁-WL7 ₁610B-617B, etc.), which collectively couples the control gates (CGs)across a specific tier, or a portion of a tier, as desired. Specifictiers in the 3D memory array, and accordingly, specific memory cells ina string, can be accessed or controlled using respective access lines.Groups of select gates can be accessed using various select lines. Forexample, first-third A₀ SGD 626A₀-628A₀ can be accessed using an A₀ SGDline SGDA₀ 625A₀, first-third A_(n) SGD 626A_(n)-628A_(n) can beaccessed using an A_(n) SGD line SGDA_(n) 625A_(n), first-third B₀ SGD626B₀-628B₀ can be accessed using a B₀ SGD line SGDB₀ 625B₀, andfirst-third B_(n) SGD 626B_(n)-628B_(n) can be accessed using a B_(n)SGD line SGDB_(n) 625B_(n). First-third A₀ SGS 631A₀-633A₀ andfirst-third A_(n) SGS 631A_(n)-633A_(n) can be accessed using a gateselect line SGS₀ 630A, and first-third B₀ SGS 631B₀-633B₀ andfirst-third B_(n) SGS 631B_(n)-633B_(n) can be accessed using a gateselect line SGS₁ 630B.

In an example, the memory array 600 can include a number of levels ofsemiconductor material (e.g., polysilicon, etc.) configured to couplethe control gates (CGs) of each memory cell or select gate (or a portionof the CGs or select gates) of a respective tier of the array. Specificstrings of memory cells in the array can be accessed, selected, orcontrolled using a combination of bit lines (BLs) and select gates,etc., and specific memory cells at one or more tiers in the specificstrings can be accessed, selected, or controlled using one or moreaccess lines (e.g., word lines).

In a NAND architecture semiconductor memory array, the state of aselected memory cell can be accessed by sensing a current or voltagevariation associated with a particular data line containing the selectedmemory cell. The memory array 600 can be accessed (e.g., by a controlcircuit, one or more processors, digital logic, etc.) using one or moredriver circuits. In an example, one or more driver circuits can activatea specific memory cell, or set of memory cells, by driving a particularpotential to one or more data lines (e.g., bit lines BL0-BL2), accesslines (e.g., word lines WL0-WL7), or select gates, depending on the typeof operation desired to be performed on the specific memory cell or setof memory cells.

To program or write data to a memory cell, a programming voltage (Vpgm)(e.g., one or more programming pulses, etc.) can be applied to selectedword lines (e.g., WL4 ₀), and thus, to a control gate of each memorycell coupled to the selected word lines. Programming pulses can begin,for example, at or near 15V, and, in certain examples, can increase inmagnitude during each programming pulse application. While the programvoltage is applied to the selected word lines, a potential, such as aground potential (e.g., Vss), can be applied to the data lines (e.g.,bit lines) and substrates (and thus the channels, between the sourcesand drains) of the memory cells targeted for programming, resulting in acharge transfer (e.g., direct injection or Fowler-Nordheim (FN)tunneling, etc.) from the channels to the floating gates of the targetedmemory cells.

In contrast, a pass voltage (Vpass) can be applied to one or more wordlines having memory cells that are not targeted for programming, or aninhibit voltage (e.g., Vcc) can be applied to data lines (e.g., bitlines) having memory cells that are not targeted for programming, forexample, to inhibit charge from being transferred from the channels tothe floating gates of such non-targeted memory cells. The pass voltagecan be variable, depending, for example, on the proximity of the appliedpass voltages to a word line targeted for programming. The inhibitvoltage can include a supply voltage (Vcc), such as a voltage from anexternal source or supply (e.g., a battery, an AC-to-DC converter,etc.), relative to a ground potential (e.g., Vss).

As an example, if a programming voltage (e.g., 15V or more) is appliedto a specific word line, such as WL4 ₀, a pass voltage of 10V can beapplied to one or more other word lines, such as WL3 ₀, WL5 ₀, etc., toinhibit programming of non-targeted memory cells, or to retain thevalues stored on such memory cells not targeted for programming. As thedistance between an applied program voltage and the non-targeted memorycells increases, the pass voltage required to refrain from programmingthe non-targeted memory cells can decrease. For example, where aprogramming voltage of 15V is applied to WL4 ₀, a pass voltage of 10Vcan be applied to WL3 ₀ and WL5 ₀, a pass voltage of 8V can be appliedto WL2 ₀ and WL6 ₀, a pass voltage of 7V can be applied to WL1 ₀ and WL7₀, etc. In other examples, the pass voltages, or number of word lines,etc., can be higher or lower, or more or less.

Sense amplifiers can be coupled to one or more of the data lines (e.g.,first, second, or third bit lines (BL0-BL2) 620-622), can detect thestate of each memory cell in respective data lines by sensing a voltageor current on a particular data line.

Between applications of one or more programming pulses (e.g., Vpgm), averify operation can be performed to determine if a selected memory cellhas reached its intended programmed state. If the selected memory cellhas reached its intended programmed state, it can be inhibited fromfurther programming. If the selected memory cell has not reached itsintended programmed state, additional programming pulses can be applied.If the selected memory cell has not reached its intended programmedstate after a particular number of programming pulses (e.g., a maximumnumber), the selected memory cell, or a string, block, or pageassociated with such selected memory cell, can be marked as defective.

To erase a memory cell or a group of memory cells (e.g., erasure istypically performed in blocks or sub-blocks), an erasure voltage (Vers)(e.g., typically Vpgm) can be applied to the substrates (and thus thechannels, between the sources and drains) of the memory cells targetedfor erasure (e.g., using one or more bit lines, select gates, etc.),while the word lines of the targeted memory cells are kept at apotential, such as a ground potential (e.g., Vss), resulting in a chargetransfer (e.g., direct injection or Fowler-Nordheim (FN) tunneling,etc.) from the floating gates of the targeted memory cells to thechannels.

FIG. 7 illustrates an example block diagram of a memory device 700including a memory array 702 having a plurality of memory cells 704, andone or more circuits or components to provide communication with, orperform one or more memory operations on, the memory array 702. Althoughshown with a single memory array 702, in other examples, one or moreadditional memory arrays, dies, or LUNs can be included herein. Incertain examples, in a storage system having a number of dies or LUNs,the memory device 700 can represent a block diagram of circuits andcomponents for each die or LUN. The memory device 700 can include a rowdecoder 712, a column decoder 714, sense amplifiers 720, a page buffer722, a selector 724, an input/output (I/O) circuit 726, a memory controlunit 730, and one or more driver circuits configured to provide a biassignal to one or more signal lines (e.g., one or more access lines 706,one or more data lines 710, etc.). In an example, the row decoder 712and the column decoder 714 can include one or more driver circuits.

The memory cells 704 of the memory array 702 can be arranged in blocks,such as first and second blocks 702A, 702B. Each block can includesub-blocks. For example, the first block 702A can include first andsecond sub-blocks 702A₀, 702A_(n), and the second block 702B can includefirst and second sub-blocks 702B₀, 702B_(n). Each sub-block can includea number of physical pages, each page including a number of memory cells704. Although illustrated herein as having two blocks, each block havingtwo sub-blocks, and each sub-block having a number of memory cells 704,in other examples, the memory array 702 can include more or fewerblocks, sub-blocks, memory cells, etc. In other examples, the memorycells 704 can be arranged in a number of rows, columns, pages,sub-blocks, blocks, etc., and accessed using, for example, access lines706, first data lines 710, or one or more select gates, source lines,etc. In certain examples, the memory device 700 can include one or moreblock select circuits configured to select one or more blocks orsub-blocks of the memory array 702.

The memory control unit 730 can control memory operations of the memorydevice 700 according to one or more signals or instructions received oncontrol lines 732, including, for example, one or more clock signals orcontrol signals that indicate a desired operation (e.g., write, read,erase, etc.), or address signals (A0-AX) received on one or more addresslines 716. One or more devices external to the memory device 700 cancontrol the values of the control signals on the control lines 732, orthe address signals on the address line 716. Examples of devicesexternal to the memory device 700 can include, but are not limited to, ahost, a memory controller, a processor, or one or more circuits orcomponents not illustrated in FIG. 7.

The memory device 700 can use access lines 706 and first data lines 710to transfer data to (e.g., write or erase) or from (e.g., read) one ormore of the memory cells 704. The row decoder 712 and the column decoder714 can receive and decode the address signals (A0-AX) from the addressline 716, can determine which of the memory cells 704 are to beaccessed, and can provide signals to one or more of the access lines 706(e.g., one or more of a plurality of word lines (WL0-WLm)) or the firstdata lines 710 (e.g., one or more of a plurality of bit lines(BL0-BLn)), such as described above.

The memory device 700 can include sense circuitry, such as the senseamplifiers 720, configured to determine the values of data on (e.g.,read), or to determine the values of data to be written to, the memorycells 704 using the first data lines 710. For example, in a selectedstring of memory cells 704, one or more of the sense amplifiers 720 canread a logic level in the selected memory cell 704 in response to a readcurrent flowing in the memory array 702 through the selected string tothe data lines 710.

One or more devices external to the memory device 700 can communicatewith the memory device 700 using the I/O lines (DQ0-DQN) 708, addresslines 716 (A0-AX), or control lines 732. The input/output (I/O) circuit726 can transfer values of data in or out of the memory device 700, suchas in or out of the page buffer 722 or the memory array 702, using theI/O lines 708, according to, for example, the control lines 732 andaddress lines 716. The page buffer 722 can store data received from theone or more devices external to the memory device 700 before the data isprogrammed into relevant portions of the memory array 702, or can storedata read from the memory array 702 before the data is transmitted tothe one or more devices external to the memory device 700.

The column decoder 714 can receive and decode address signals (A0-AX)into one or more column select signals (CSEL1-CSELn). The selector 724(e.g., a select circuit) can receive the column select signals(CSEL1-CSELn) and select data in the page buffer 722 representing valuesof data to be read from or to be programmed into memory cells 704.Selected data can be transferred between the page buffer 722 and the I/Ocircuit 726 using second data lines 718.

The memory control unit 730 can receive positive and negative supplysignals, such as a supply voltage (Vcc) 734 and a negative supply (Vss)736 (e.g., a ground potential), from an external source or supply (e.g.,an internal or external battery, an AC-to-DC converter, etc.). Incertain examples, the memory control unit 730 can include a regulator728 to internally provide positive or negative supply signals.

FIG. 8 illustrates a block diagram of an example machine 800 upon whichany one or more of the techniques (e.g., methodologies) discussed hereinmay perform, such as triggering a CSAVE operation in a memory device(e.g., an NVDIMM) using a timer implemented using a memory controller ofthe NVDIMM. In alternative embodiments, the machine 800 may operate as astandalone device or may be connected (e.g., networked) to othermachines. In a networked deployment, the machine 800 may operate in thecapacity of a server machine, a client machine, or both in server-clientnetwork environments. In an example, the machine 800 may act as a peermachine in peer-to-peer (P2P) (or other distributed) networkenvironment. The machine 800 may be a personal computer (PC), a tabletPC, a set-top box (STB), a personal digital assistant (PDA), a mobiletelephone, a web appliance, an IoT device, automotive system, or anymachine capable of executing instructions (sequential or otherwise) thatspecify actions to be taken by that machine. Further, while only asingle machine is illustrated, the term “machine” shall also be taken toinclude any collection of machines that individually or jointly executea set (or multiple sets) of instructions to perform any one or more ofthe methodologies discussed herein, such as cloud computing, software asa service (SaaS), other computer cluster configurations.

Examples, as described herein, may include, or may operate by, logic,components, devices, packages, or mechanisms. Circuitry is a collection(e.g., set) of circuits implemented in tangible entities that includehardware (e.g., simple circuits, gates, logic, etc.). Circuitrymembership may be flexible over time and underlying hardwarevariability. Circuitries include members that may, alone or incombination, perform specific tasks when operating. In an example,hardware of the circuitry may be immutably designed to carry out aspecific operation (e.g., hardwired). In an example, the hardware of thecircuitry may include variably connected physical components (e.g.,execution units, transistors, simple circuits, etc.) including acomputer-readable medium physically modified (e.g., magnetically,electrically, moveable placement of invariant massed particles, etc.) toencode instructions of the specific operation. In connecting thephysical components, the underlying electrical properties of a hardwareconstituent are changed, for example, from an insulator to a conductoror vice versa. The instructions enable participating hardware (e.g., theexecution units or a loading mechanism) to create members of thecircuitry in hardware via the variable connections to carry out portionsof the specific tasks when in operation. Accordingly, thecomputer-readable medium is communicatively coupled to the othercomponents of the circuitry when the device is operating. In an example,any of the physical components may be used in more than one member ofmore than one circuitry. For example, under operation, execution unitsmay be used in a first circuit of a first circuitry at one point in timeand reused by a second circuit in the first circuitry, or by a thirdcircuit in a second circuitry at a different time.

The machine (e.g., computer system) 800 (e.g., the host 105, the storagesystem 110, etc.) may include a hardware processor 802 (e.g., a centralprocessing unit (CPU), a graphics processing unit (GPU), a hardwareprocessor core, or any combination thereof, such as a memory controller,etc.), a main memory 804 and a static memory 806, some or all of whichmay communicate with each other via an interlink (e.g., bus) 830. Themachine 800 may further include a display unit, an alphanumeric inputdevice (e.g., a keyboard), and a user interface (UI) navigation device(e.g., a mouse). In an example, the display unit, input device and UInavigation device may be a touch screen display. The machine 800 mayadditionally include a signal generation device (e.g., a speaker), anetwork interface device 808, and one or more sensors, such as a globalpositioning system (GPS) sensor, compass, accelerometer, or othersensor. The machine 800 may include an output controller, such as aserial (e.g., Universal Serial Bus (USB), parallel, or other wired orwireless (e.g., infrared (IR), near field communication (NFC), etc.)connection to communicate or control one or more peripheral devices(e.g., a printer, card reader, etc.).

The machine 800 may include a storage system (e.g., a machine-readablemedium) on which is stored one or more sets of data structures orinstructions 826 (e.g., software) embodying or utilized by any one ormore of the techniques or functions described herein. The instructions826 may also reside, completely or at least partially, within the mainmemory 804, within static memory 806, or within the hardware processor802 during execution thereof by the machine 800. In an example, one orany combination of the hardware processor 802, the main memory 804, thestatic memory 806, or the storage system 818 may constitute amachine-readable medium. The term “machine-readable medium” may includea single medium or multiple media (e.g., a centralized or distributeddatabase, or associated caches and servers) configured to store the oneor more instructions 826.

The term “machine-readable medium” may include any medium that iscapable of storing, encoding, or carrying instructions for execution bythe machine 800 and that cause the machine 800 to perform any one ormore of the techniques of the present disclosure, or that is capable ofstoring, encoding, or carrying data structures used by or associatedwith such instructions. Non-limiting machine-readable medium examplesmay include solid-state memories, and optical and magnetic media. In anexample, a massed machine-readable medium comprises a machine-readablemedium with a plurality of particles having invariant (e.g., rest) mass.Accordingly, massed machine-readable media are not transitorypropagating signals. Specific examples of massed machine-readable mediamay include: non-volatile memory, such as semiconductor memory devices(e.g., Electrically Programmable Read-Only Memory (EPROM), ElectricallyErasable Programmable Read-Only Memory (EEPROM)) and flash memorydevices; magnetic disks, such as internal hard disks and removabledisks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

The instructions 826 (e.g., software, programs, an operating system(OS), etc.) or other data are stored on the storage system 818, can beaccessed by the memory 804 for use by the processor 802. The memory 804(e.g., DRAM) is typically fast, but volatile, and thus a different typeof storage than the storage system 818 (e.g., an SSD), which is suitablefor long-term storage, including while in an “off” condition. Theinstructions 826 or data in use by a user or the machine 800 aretypically loaded in the memory 804 for use by the processor 802. Whenthe memory 804 is full, virtual space from the storage system 818 can beallocated to supplement the memory 804; however, because the storagesystem 818 device is typically slower than the memory 804, and writespeeds are typically at least twice as slow as read speeds, use ofvirtual memory can greatly reduce user experience due to storage devicelatency (in contrast to the memory 804, e.g., DRAM). Further, use of thestorage system 818 for virtual memory can greatly reduce the usablelifespan of the storage system 818.

In contrast to virtual memory, virtual memory compression (e.g., theLinux™ kernel feature “ZRAM”) uses part of the memory as compressedblock storage to avoid paging to the storage system 818. Paging takesplace in the compressed block until it is necessary to write such datato the storage system 818. Virtual memory compression increases theusable size of memory 804, while reducing wear on the storage system818.

Storage systems optimized for mobile electronic devices, or mobilestorage, traditionally include MMC solid-state storage systems (e.g.,micro Secure Digital (microSD™) cards, etc.). MMC devices include anumber of parallel interfaces (e.g., an 8-bit parallel interface) with ahost, and are often removable and separate components from the host. Incontrast, eMMC™ devices are attached to a circuit board and considered acomponent of the host, with read speeds that rival serial ATA™ (SerialAT (Advanced Technology) Attachment, or SATA) based SSD devices.However, demand for mobile device performance continues to improve, suchas to fully enable virtual or augmented-reality devices, utilizeincreasing networks speeds, etc. In response to this demand, storagesystems have shifted from parallel to serial communication interfaces.Universal Flash Storage (UFS) devices, including controllers andfirmware, communicate with a host using a low-voltage signalinginterface, such as a Scalable Low-Voltage Signaling (SLVS) interfacewith dedicated read/write paths, further increasing read/write speeds.

The instructions 826 may further be transmitted or received over acommunications network 820 using a transmission medium via the networkinterface device 808 utilizing any one of a number of transfer protocols(e.g., frame relay, internet protocol (IP), transmission controlprotocol (TCP), user datagram protocol (UDP), hypertext transferprotocol (HTTP), etc.). Example communication networks may include alocal area network (LAN), a wide area network (WAN), a packet datanetwork (e.g., the Internet), mobile telephone networks (e.g., cellularnetworks), Plain Old Telephone (POTS) networks, and wireless datanetworks (e.g., Institute of Electrical and Electronics Engineers (IEEE)802.11 family of standards known as Wi-Fi™, IEEE 802.16 family ofstandards known as WiMax®), IEEE 802.15.4 family of standards,peer-to-peer (P2P) networks, among others. In an example, the networkinterface device 808 may include one or more physical jacks (e.g.,Ethernet, coaxial, or phone jacks) or one or more antennas to connect tothe communications network 820. In an example, the network interfacedevice 808 may include a plurality of antennas to wirelessly communicateusing at least one of single-input multiple-output (SIMO),multiple-input multiple-output (MIMO), or multiple-input single-output(MISO) techniques. The term “transmission medium” shall be taken toinclude any intangible medium that is capable of storing, encoding, orcarrying instructions for execution by the machine 800, and includesdigital or analog communications signals or other intangible medium tofacilitate communication of such software.

In Example 1, subject matter (e.g., a system) may comprise a storagesystem having an active state and a standby state, the standby statehaving a limited maximum standby current allowance, the storage systemcomprising: a standby voltage generator circuit having a refresh periodand an active period, the standby voltage generator circuit including: avoltage generator configured to receive an internal low-voltage sourceof the storage system in the standby state and to provide a high-voltagebias signal in the active period of the standby state without exceedingthe limited maximum standby current allowance; and a voltage generatorcontrol circuit configured to control transitions between the refreshand active periods in the standby state, wherein the refresh period islonger than the active period.

In Example 2, the subject matter of Example 1 may optionally beconfigured such that the voltage generator is configured to provide thehigh-voltage bias signal to enable a string driver circuit of thestorage system to couple a global word line of a memory device to alocal word line of the memory device of the storage device withoutexceeding the limited maximum standby current allowance.

In Example 3, the subject matter of any one or more of Examples 1-2 mayoptionally comprise a string driver circuit configured to isolate theglobal word line from the local word line of the memory device in afirst state, and to couple the global word line to the local word linein a second state; and a standby bias generator with sinking andsourcing capabilities configured to provide a positive bias to theglobal word line in the standby state.

In Example 4, the subject matter of any one or more of Examples 1-3 mayoptionally be configured such that the positive bias comprises alow-voltage positive bias configured to sink voltage from a pillar of astring of memory cells coupled to the local word line to reduce readdisturbance errors in the standby state.

In Example 5, the subject matter of any one or more of Examples 1-4 mayoptionally be configured such that the standby voltage generator circuitis enabled in the standby state and disabled in the active state.

In Example 6, the subject matter of any one or more of Examples 1-5 mayoptionally comprise separate first and second oscillators, the firstoscillator configured to consume less power than the second oscillator,wherein the standby voltage generator is configured to use the firstoscillator in the refresh period and the second oscillator in the activeperiod.

In Example 7, the subject matter of any one or more of Examples 1-6 mayoptionally be configured such that the voltage generator control circuitis configured to receive a clock signal from the first oscillator in therefresh period, to increment a first count using the received clocksignal, to compare the first count to a first threshold, and to controltransitions from the refresh period to the active period using thecomparison.

In Example 8, the subject matter of any one or more of Examples 1-7 mayoptionally be configured such that the voltage generator control circuitis configured to control a time of one or more of the refresh period orthe active period using a number of selectable trim values.

In Example 9, the subject matter of any one or more of Examples 1-8 mayoptionally be configured such that the low-voltage internal sourcecomprises a low-voltage internal VCC in the storage system in thestandby state.

In Example 10, the subject matter of any one or more of Examples 1-9 mayoptionally be configured such that the storage system comprises: amemory device comprising an array of non-volatile memory cells andmultiple local word lines, each local word line configured to provideaccess to multiple memory cells in the active state of the storagesystem; and a memory controller configured to receive instructions froma host device and to control operations on the memory device in theactive state of the storage system.

In Example 11, subject matter (e.g., a method) may comprise: receivingan internal low-voltage source of a storage system at an input of astandby voltage generator circuit in a standby state of the storagesystem, the standby voltage generator circuit having a refresh periodand an active period; providing a high-voltage bias signal at an outputof the standby voltage generator circuit in the active period of thestandby state without exceeding a limited maximum standby currentallowance of the standby state; and controlling transitions between therefresh and active periods in the standby state of the storage systemusing a voltage generator control circuit, wherein the refresh period islonger than the active period.

In Example 12, the subject matter of Example 11 may optionally compriseenabling a string driver circuit of the storage system to couple aglobal word line of the storage device to a local word line of a memorydevice of the storage device using the high-voltage bias signal withoutexceeding the limited maximum standby current allowance.

In Example 13, the subject matter of any one or more of Examples 11-12may optionally comprise: isolating a global word line from a local wordline of a memory device using a first state of the string driver;coupling the global word line to the local word line using a secondstate of the string driver, wherein enabling the string driver circuitto couple the global word line to the local word line comprises usingthe second state; and providing a positive bias to the global word linein the standby state using a standby bias generator with sinking andsourcing capabilities.

In Example 14, the subject matter of any one or more of Examples 11-13may optionally be configured such that the positive bias comprises alow-voltage positive bias configured to sink voltage from, or bias, apillar of a string of memory cells coupled to the local word line toreduce read disturbance errors in the standby state.

In Example 15, the subject matter of any one or more of Examples 11-14may optionally comprise: enabling the standby voltage generator circuitin the standby state of the storage system; and disabling the standbyvoltage generator circuit in an active state of the storage system.

In Example 16, the subject matter of any one or more of Examples 11-15may optionally be configured such that controlling transitions betweenthe refresh and active periods comprises: controlling transitions fromthe refresh period to the active period using a first oscillator; andcontrolling transitions from the active period to the refresh periodusing a second oscillator, separate from the first oscillator, whereinthe first oscillator includes a low-power oscillator configured toconsume less power than the second oscillator.

In Example 17, the subject matter of any one or more of Examples 11-16may optionally be configured such that controlling transitions from therefresh period to the active period comprises: receiving a clock signalfrom the first oscillator in the refresh period; incrementing a firstcount using the received clock signal; comparing the first count to afirst threshold; and controlling transitions from the refresh period tothe active period using the comparison.

In Example 18, the subject matter of any one or more of Examples 11-17may optionally comprise controlling a time of one or more of the refreshperiod or the active period using a number of selectable trim values.

In Example 19, the subject matter of any one or more of Examples 11-18may optionally be configured such that the low-voltage internal sourcecomprises a low-voltage internal VCC in the storage system in thestandby state.

In Example 20, the subject matter of any one or more of Examples 11-19may optionally comprise: providing access to a number of memory cellsresponsive to a bias condition of a respective local word line of amemory device in an active state of the storage system; and receivinginstructions from a host device and controlling operations on the memorydevice in the active state of the storage system.

In Example 21, subject matter (e.g., a system or apparatus) mayoptionally combine any portion or combination of any portion of any oneor more of Examples 1-20 to comprise “means for” performing any portionof any one or more of the functions or methods of Examples 1-20, or a“non-transitory machine-readable medium” including instructions that,when performed by a machine, cause the machine to perform any portion ofany one or more of the functions or methods of Examples 1-20.

The above detailed description includes references to the accompanyingdrawings, which form a part of the detailed description. The drawingsshow, by way of illustration, specific embodiments in which theinvention can be practiced. These embodiments are also referred toherein as “examples”. Such examples can include elements in addition tothose shown or described. However, the present inventors alsocontemplate examples in which only those elements shown or described areprovided. Moreover, the present inventors also contemplate examplesusing any combination or permutation of those elements shown ordescribed (or one or more aspects thereof), either with respect to aparticular example (or one or more aspects thereof), or with respect toother examples (or one or more aspects thereof) shown or describedherein.

In this document, the terms “a” or “an” are used, as is common in patentdocuments, to include one or more than one, independent of any otherinstances or usages of “at least one” or “one or more.” In thisdocument, the term “or” is used to refer to a nonexclusive or, such that“A or B” may include “A but not B,” “B but not A,” and “A and B,” unlessotherwise indicated. In the appended claims, the terms “including” and“in which” are used as the plain-English equivalents of the respectiveterms “comprising” and “wherein”. Also, in the following claims, theterms “including” and “comprising” are open-ended. A system, device,article, or process that includes elements in addition to those listedafter such a term in a claim are still deemed to fall within the scopeof that claim. Moreover, in the following claims, the terms “first,”“second,” and “third,” etc. are used merely as labels, and are notintended to impose numerical requirements on their objects.

In various examples, the components, controllers, processors, units,engines, or tables described herein can include, among other things,physical circuitry or firmware stored on a physical device. As usedherein, “processor” means any type of computational circuit such as, butnot limited to, a microprocessor, a microcontroller, a graphicsprocessor, a digital signal processor (DSP), or any other type ofprocessor or processing circuit, including a group of processors ormulti-core devices.

Operating a memory cell, as used herein, includes reading from, writingto, or erasing the memory cell. The operation of placing a memory cellin an intended state is referred to herein as “programming,” and caninclude both writing to or erasing from the memory cell (e.g., thememory cell may be programmed to an erased state).

According to one or more embodiments of the present disclosure, a memorycontroller (e.g., a processor, controller, firmware, etc.) locatedinternal or external to a memory device, is capable of determining(e.g., selecting, setting, adjusting, computing, changing, clearing,communicating, adapting, deriving, defining, utilizing, modifying,applying, etc.) a quantity of wear cycles, or a wear state (e.g.,recording wear cycles, counting operations of the memory device as theyoccur, tracking the operations of the memory device it initiates,evaluating the memory device characteristics corresponding to a wearstate, etc.)

According to one or more embodiments of the present disclosure, a memoryaccess device may be configured to provide wear cycle information to thememory device with each memory operation. The memory device controlcircuitry (e.g., control logic) may be programmed to compensate formemory device performance changes corresponding to the wear cycleinformation. The memory device may receive the wear cycle informationand determine one or more operating parameters (e.g., a value,characteristic) in response to the wear cycle information.

It will be understood that when an element is referred to as being “on,”“connected to,” or “coupled with” another element, it can be directlyon, connected, or coupled with the other element or intervening elementsmay be present. In contrast, when an element is referred to as being“directly on,” “directly connected to,” or “directly coupled with”another element, there are no intervening elements or layers present. Iftwo elements are shown in the drawings with a line connecting them, thetwo elements can be either be coupled, or directly coupled, unlessotherwise indicated.

Method examples described herein can be machine, device, orcomputer-implemented at least in part. Some examples can include acomputer-readable medium, a device-readable medium, or amachine-readable medium encoded with instructions operable to configurean electronic device to perform methods as described in the aboveexamples. An implementation of such methods can include code, such asmicrocode, assembly language code, a higher-level language code, or thelike. Such code can include computer readable instructions forperforming various methods. The code may form portions of computerprogram products. Further, the code can be tangibly stored on one ormore volatile or non-volatile tangible computer-readable media, such asduring execution or at other times. Examples of these tangiblecomputer-readable media can include, but are not limited to, hard disks,removable magnetic disks, removable optical disks (e.g., compact discsand digital video disks), magnetic cassettes, memory cards or sticks,random-access memories (RAMs), read-only memories (ROMs), solid-statedrives (SSDs), Universal Flash Storage (UFS) device, embedded MMC (eMMC)device, and the like.

The above description is intended to be illustrative, and notrestrictive. For example, the above-described examples (or one or moreaspects thereof) may be used in combination with each other. Otherembodiments can be used, such as by one of ordinary skill in the artupon reviewing the above description. It is submitted with theunderstanding that it will not be used to interpret or limit the scopeor meaning of the claims. Also, in the above Detailed Description,various features may be grouped together to streamline the disclosure.This should not be interpreted as intending that an unclaimed disclosedfeature is essential to any claim. Rather, inventive subject matter maylie in less than all features of a particular disclosed embodiment.Thus, the following claims are hereby incorporated into the DetailedDescription, with each claim standing on its own as a separateembodiment, and it is contemplated that such embodiments can be combinedwith each other in various combinations or permutations. The scope ofthe invention should be determined with reference to the appendedclaims, along with the full scope of equivalents to which such claimsare entitled.

1. A storage system having an active state and a standby state, thestandby state having an active period and a refresh period, the storagesystem comprising: an active voltage generator circuit configured togenerate a high-voltage source in the active state and to be disabled inthe standby state; a standby voltage generator circuit configured toreceive an internal low-voltage source of the storage system in therefresh period of the standby state and to provide a high-voltage biassignal in the active period of the standby state; and a standby biasgenerator configured to provide a low-voltage positive bias to a globalword line of a memory device of the storage system to sink voltage fromthe memory device in the standby state to reduce read disturbance errorsin the memory device.
 2. The storage system of claim 1, comprising: avoltage generator control circuit configured to control transitionsbetween the refresh and active periods of the standby state, wherein therefresh period is longer than the active period.
 3. The storage systemof claim 2, wherein the voltage generator control circuit is configuredto control a time of one or more of the refresh period or the activeperiod using a number of selectable trim values.
 4. The storage systemof claim 1, comprising: a string driver circuit configured to isolatethe global word line of the memory device from a local word line of thememory device in a first state and to couple the global word line to thelocal word line in a second state.
 5. The storage system of claim 4,wherein the standby voltage generator circuit is configured to providethe high-voltage bias signal to enable the string driver circuit of thestorage system to couple the global word line of the memory device tothe local word line of the memory device without exceeding a limitedmaximum standby current allowance of the storage system.
 6. The storagesystem of claim 4, wherein the standby bias generator is configured toprovide the low-voltage positive bias to sink voltage from a pillar of astring of memory cells coupled to the local word line of the memorydevice in the standby state to reduce read disturbance errors in thememory device.
 7. The storage system of claim 1, comprising: separatefirst and second oscillators, the first oscillator configured to consumeless power than the second oscillator, wherein the standby voltagegenerator is configured to use the first oscillator in the refreshperiod and the second oscillator in the active period.
 8. The storagesystem of claim 1, wherein the storage system comprises: the memorydevice comprising an array of non-volatile memory cells and multiplelocal word lines, each local word line configured to provide access tomultiple memory cells in the active state of the storage system; and amemory controller configured to receive instructions from a host deviceand to control operations on the memory device in the active state ofthe storage system.
 9. The storage system of claim 1, wherein theinternal low-voltage source comprises an internal low-voltage VCC of thestorage system in the standby state.
 10. A method comprising: generatinga high-voltage source in an active state of a storage system using anactive voltage generator circuit; receiving, using a standby voltagegenerator circuit, an internal low-voltage source of the storage systemin a refresh period of a standby state of the storage system; providing,using the standby voltage generator circuit, a high-voltage bias signalin an active period of the standby state of the storage system using theinternal low-voltage source of the storage system received in therefresh period; and providing, using a standby bias generator, alow-voltage positive bias to a global word line of a memory device ofthe storage system to sink voltage from the memory device in the standbystate to reduce read disturbance errors in the memory device.
 11. Themethod of claim 10, comprising: enabling the active voltage generatorcircuit in the active state; and disabling the active voltage generatorcircuit in the standby state.
 12. The method of claim 10, comprising:controlling transitions between the refresh and active periods of thestandby state using a voltage generator control circuit, wherein therefresh period is longer than the active period.
 13. The method of claim12, comprising: controlling, using the voltage generator controlcircuit, a time of one or more of the refresh period or the activeperiod using a number of selectable trim values.
 14. The method of claim12, wherein controlling transitions between the refresh and activeperiods comprises: controlling transitions from the refresh period tothe active period using a first oscillator; and controlling transitionsfrom the active period to the refresh period using a second oscillator,separate from the first oscillator, wherein the first oscillator isconfigured to consume less power than the second oscillator.
 15. Themethod of claim 14, wherein controlling transitions from the refreshperiod to the active period comprises: receiving a clock signal from thefirst oscillator in the refresh period; incrementing a first count usingthe received clock signal; comparing the first count to a firstthreshold; and controlling transitions from the refresh period to theactive period using the comparison.
 16. The method of claim 10,comprising: isolating, using a string driver circuit, the global wordline of the memory device from a local word line of the memory device ina first state and to couple the global word line to the local word linein a second state.
 17. The method of claim 16, wherein providing thehigh-voltage bias signal comprises to enable the string driver circuitof the storage system to couple the global word line of the memorydevice to the local word line of the memory device without exceeding alimited maximum standby current allowance of the storage system.
 18. Themethod of claim 16, wherein providing the low-voltage positive biascomprises to sink voltage from a pillar of a string of memory cellscoupled to the local word line of the memory device in the standby stateto reduce read disturbance errors in the memory device.
 19. The methodof claim 10, wherein the storage system comprises: the memory devicecomprising an array of non-volatile memory cells and multiple local wordlines, each local word line configured to provide access to multiplememory cells in the active state of the storage system; and a memorycontroller configured to receive instructions from a host device and tocontrol operations on the memory device in the active state of thestorage system.
 20. The method of claim 10, wherein the internallow-voltage source comprises an internal low-voltage VCC of the storagesystem in the standby state.